In a computer (data processing device), a system controller is used in connecting semiconductor devices such as a CPU, memory, etc. FIG. 1 illustrates the configuration of the data processing device designed by connecting a plurality of semiconductor devices to the system controller. In the data processing device, as illustrated in FIG. 1, each of a CPU 50, memory 60, and an I/O controller 70 is connected to a system controller 80. The I/O controller 70 controls a storage device such as a hard disk device, an optical disk device, etc., or communicates with an external device. Each semiconductor device of the memory 60 and the I/O controller 70 corresponds to an external device to the system controller 80.
Between connected semiconductor devices, internal clocks are not synchronous with each other in many cases. Therefore, it is common that a semiconductor device is loaded with a synchronization circuit as illustrated in FIG. 2. In FIG. 2, two connected semiconductor devices are expressed as “CHIP”. A buffer 91 stores a packet (data) to be transferred to a semiconductor device 100. A pointer 92 points to the buffer 91 storing a packet provided from inside a semiconductor device 90. A decoder 93 decodes a point value outputted by the pointer 92, and stores a packet in the buffer 91 corresponding to the point value. A selector 94 selects one of the packets stored in the buffer 91. A pointer 95 specifies a packet to be selected by the selector 94. A buffer 96 stores a packet outputted by the selector 94. A component operating with an internal clock is indicated by dots. A component without dots operates with a clock of a transmission line etc. (hereinafter referred to as an “interface clock”). It is clear from FIG. 2, the part of the interface for the outside operates with low speed.
When an interface between semiconductor devices is verified (tested), it is necessary that a target semiconductor device, that is, a semiconductor device whose interface is used in transferring a packet, is connected. Some semiconductor devices require another device (for example, a storage device) to be connected. However, immediately after a semiconductor device has newly appeared on the market, there can be normally a case where a target semiconductor device cannot be appropriately connected, or a case where a device located prior to a target semiconductor device cannot be appropriately connected. In these cases, the verification of the interface between the semiconductor devices is delayed, thereby imposing undesired effects on the processes. For example, in the data processing device illustrated in FIG. 1, accessing from the CPU 50 to the memory 60 and accessing from the I/O controller 70 to the memory 60 are the main data flows. However, when the I/O controller 70 cannot be connected, the interface between the system controller 80 and the I/O controller 70 cannot be verified. Thus, it is important to be able to verify an interface to some extent.
The interface can also be verified by connecting after externally arranging a plurality of other devices other than a semiconductor device (Japanese Published Patent Application No. S60-171848). However, in the conventional method, the entire device becomes upsized to perform verification, and very costly. Therefore, it is important to perform the verification at a lower cost.